The present invention relates to adjusting a signal eye, and more specifically, to adjusting the signal eye upon identifying a target chip coupled to bus shared by multiple chips.
When designing traditional DDR3 fly-by nets, control settings such as the I/O impedance and slew rate of a driver are set depending on the distances of the DRAM modules from the driver. Generally, for an increasing number of loads on a fly-by net, the driver impedance is set lower and the slew rate is set higher. If the DRAM modules are too close (electrically) to the driver, the received signal at these modules may have a poor signal eye which results in incorrectly latched data. The typical solution is to add electrical length between the driver and the first DRAM module on the net, which causes the chain of DRAM modules to appear more like a single load from the perspective of the driver. Although this improves the signal quality at the DRAM module closest to the driver, the extra trace length causes more attenuation in the signal as it propagates down the net. As a result, the last DRAM module on the net may receive a degraded signal eye that is below receiver thresholds. As data transmission rates increase, identifying suitable control settings that permit all the DRAM modules on the fly-by net to properly receive the signal becomes a difficult, if not impossible task.